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vr4300_asm.h
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1
7#ifndef VR4300_ASM_H__
8#define VR4300_ASM_H__
9
10#include <stdint.h>
11
17typedef union {
18 uint32_t raw;
20 struct {
21 uint32_t op : 6;
22 uint32_t rs : 5;
23 uint32_t rt : 5;
24 uint32_t imm : 16;
25 } i_type;
27 struct {
28 uint32_t op : 6;
29 uint32_t target : 26;
30 } j_type;
32 struct {
33 uint32_t op : 6;
34 uint32_t rs : 5;
35 uint32_t rt : 5;
36 uint32_t rd : 5;
37 uint32_t sa : 5;
38 uint32_t funct : 6;
39 } r_type;
41 struct {
42 uint32_t op : 6;
43 uint32_t co : 1;
44 uint32_t funct : 25;
45 } c_type;
46} vr4300_instruction_t;
47
53typedef enum {
54 OP_SPECIAL,
55 OP_REGIMM,
56 OP_J,
57 OP_JAL,
58 OP_BEQ,
59 OP_BNE,
60 OP_BLEZ,
61 OP_BGTZ,
62 OP_ADDI,
63 OP_ADDIU,
64 OP_SLTI,
65 OP_SLTIU,
66 OP_ANDI,
67 OP_ORI,
68 OP_XORI,
69 OP_LUI,
70 OP_COP0,
71 OP_COP1,
72 OP_COP2,
73 __OP_RESERVED_19,
74 OP_BEQL,
75 OP_BNEL,
76 OP_BLEZL,
77 OP_BGTZL,
78 OP_DADDI,
79 OP_DADDIU,
80 OP_LDL,
81 OP_LDR,
82 __OP_RESERVED_28,
83 __OP_RESERVED_29,
84 __OP_RESERVED_30,
85 __OP_RESERVED_31,
86 OP_LB,
87 OP_LH,
88 OP_LWL,
89 OP_LW,
90 OP_LBU,
91 OP_LHU,
92 OP_LWR,
93 OP_LWU,
94 OP_SB,
95 OP_SH,
96 OP_SWL,
97 OP_SW,
98 OP_SDL,
99 OP_SDR,
100 OP_SWR,
101 OP_CACHE,
102 OP_LL,
103 OP_LWC1,
104 OP_LWC2,
105 __OP_RESERVED_51,
106 OP_LLD,
107 OP_LDC1,
108 OP_LDC2,
109 OP_LD,
110 OP_SC,
111 OP_SWC1,
112 OP_SWC2,
113 __OP_RESERVED_59,
114 OP_SCD,
115 OP_SDC1,
116 OP_SDC2,
117 OP_SD,
118} vr4300_op_t;
119
120typedef enum {
121 FUNCT_SSL,
122 __FUNCT_RESERVED_1,
123 FUNCT_SRL,
124 FUNCT_SRA,
125 FUNCT_SLLV,
126 __FUNCT_RESERVED_5,
127 FUNCT_SRLV,
128 FUNCT_SRAV,
129 FUNCT_JR,
130 FUNCT_JALR,
131 __FUNCT_RESERVED_10,
132 __FUNCT_RESERVED_11,
133 FUNCT_SYSCALL,
134 FUNCT_BREAK,
135 __FUNCT_RESERVED_14,
136 FUNCT_SYNC,
137 FUNCT_MFHI,
138 FUNCT_MTHI,
139 FUNCT_MFLO,
140 FUNCT_MTLO,
141 FUNCT_DSLLV,
142 __FUNCT_RESERVED_21,
143 FUNCT_DSRLV,
144 FUNCT_DSRAV,
145 FUNCT_MULT,
146 FUNCT_MULTU,
147 FUNCT_DIV,
148 FUNCT_DIVU,
149 FUNCT_DMULT,
150 FUNCT_DMULTU,
151 FUNCT_DDIV,
152 FUNCT_DDIVU,
153 FUNCT_ADD,
154 FUNCT_ADDU,
155 FUNCT_SUB,
156 FUNCT_SUBU,
157 FUNCT_AND,
158 FUNCT_OR,
159 FUNCT_XOR,
160 FUNCT_NOR,
161 __FUNCT_RESERVED_40,
162 __FUNCT_RESERVED_41,
163 FUNCT_SLT,
164 FUNCT_SLTU,
165 FUNCT_DADD,
166 FUNCT_DADDU,
167 FUNCT_DSUB,
168 FUNCT_DSUBU,
169 FUNCT_TGE,
170 FUNCT_TGEU,
171 FUNCT_TLT,
172 FUNCT_TLTU,
173 FUNCT_TEQ,
174 __FUNCT_RESERVED_53,
175 FUNCT_TNE,
176 __FUNCT_RESERVED_55,
177 FUNCT_DSLL,
178 __FUNCT_RESERVED_57,
179 FUNCT_DSRL,
180 FUNCT_DSRA,
181 FUNCT_DSLL32,
182 __FUNCT_RESERVED_61,
183 FUNCT_DSRL32,
184 FUNCT_DSRA32,
185} vr4300_funct_t;
186
187typedef enum {
188 REGIMM_BLTZ,
189 REGIMM_BGEZ,
190 REGIMM_BLTZL,
191 REGIMM_BGEZL,
192 __REGIMM_RESERVED_4,
193 __REGIMM_RESERVED_5,
194 __REGIMM_RESERVED_6,
195 __REGIMM_RESERVED_7,
196 REGIMM_TGEI,
197 REGIMM_TGEIU,
198 REGIMM_TLTI,
199 REGIMM_TLTIU,
200 REGIMM_TEQI,
201 __REGIMM_RESERVED_13,
202 REGIMM_TNEI,
203 __REGIMM_RESERVED_15,
204 REGIMM_BLTZAL,
205 REGIMM_BGEZAL,
206 REGIMM_BLTZALL,
207 REGIMM_BGEZALL,
208 __REGIMM_RESERVED_20,
209 __REGIMM_RESERVED_21,
210 __REGIMM_RESERVED_22,
211 __REGIMM_RESERVED_23,
212 __REGIMM_RESERVED_24,
213 __REGIMM_RESERVED_25,
214 __REGIMM_RESERVED_26,
215 __REGIMM_RESERVED_27,
216 __REGIMM_RESERVED_28,
217 __REGIMM_RESERVED_29,
218 __REGIMM_RESERVED_30,
219 __REGIMM_RESERVED_31,
220} vr4300_regimm_t;
221
222typedef enum {
223 REG_ZERO,
224 REG_AT,
225 REG_V0,
226 REG_V1,
227 REG_A0,
228 REG_A1,
229 REG_A2,
230 REG_A3,
231 REG_T0,
232 REG_T1,
233 REG_T2,
234 REG_T3,
235 REG_T4,
236 REG_T5,
237 REG_T6,
238 REG_T7,
239 REG_S0,
240 REG_S1,
241 REG_S2,
242 REG_S3,
243 REG_S4,
244 REG_S5,
245 REG_S6,
246 REG_S7,
247 REG_T8,
248 REG_T9,
249 REG_K0,
250 REG_K1,
251 REG_GP,
252 REG_SP,
253 REG_FP,
254 REG_RA,
255} vr4300_reg_t;
256
257typedef enum {
258 C0_REG_INDEX,
259 C0_REG_RANDOM,
260 C0_REG_ENTRY_LO_0,
261 C0_REG_ENTRY_LO_1,
262 C0_REG_CONTEXT,
263 C0_REG_PAGE_MASK,
264 C0_REG_WIRED,
265 __C0_REG_RESERVED_7,
266 C0_REG_BAD_V_ADDR,
267 C0_REG_COUNT,
268 C0_REG_ENTRY_HI,
269 C0_REG_COMPARE,
270 C0_REG_STATUS,
271 C0_REG_CAUSE,
272 C0_REG_EPC,
273 C0_REG_PR_ID,
274 C0_REG_CONFIG,
275 C0_REG_LL_ADDR,
276 C0_REG_WATCH_LO,
277 C0_REG_WATCH_HI,
278 C0_REG_X_CONTEXT,
279 __C0_REG_RESERVED_21,
280 __C0_REG_RESERVED_22,
281 __C0_REG_RESERVED_23,
282 __C0_REG_RESERVED_24,
283 __C0_REG_RESERVED_25,
284 C0_REG_PARITY_ERROR,
285 C0_REG_CACHE_ERROR,
286 C0_REG_TAG_LO,
287 C0_REG_TAG_HI,
288 C0_REG_ERROR_EPC,
289 __C0_REG_RESERVED_31,
290} vr4300_c0_reg_t;
291
292typedef enum {
293 COPZ_RS_MF,
294 COPZ_RS_DMF,
295 COPZ_RS_CF,
296 __COPZ_RS_RESERVED_3,
297 COPZ_RS_MT,
298 COPZ_RS_DMT,
299 COPZ_RS_CT,
300 __COPZ_RS_RESERVED_7,
301 COPZ_RS_BC,
302 __COPZ_RS_RESERVED_9,
303 __COPZ_RS_RESERVED_10,
304 __COPZ_RS_RESERVED_11,
305 __COPZ_RS_RESERVED_12,
306 __COPZ_RS_RESERVED_13,
307 __COPZ_RS_RESERVED_14,
308 __COPZ_RS_RESERVED_15,
309} vr4300_copz_rs_t;
310
311typedef enum {
312 __C0_FUNCT_RESERVED_0,
313 C0_FUNCT_TLBR,
314 C0_FUNCT_TLBWI,
315 __C0_FUNCT_RESERVED_3,
316 __C0_FUNCT_RESERVED_4,
317 __C0_FUNCT_RESERVED_5,
318 C0_FUNCT_TLBWR,
319 __C0_FUNCT_RESERVED_7,
320 C0_FUNCT_TLBP,
321 __C0_FUNCT_RESERVED_9,
322 __C0_FUNCT_RESERVED_10,
323 __C0_FUNCT_RESERVED_11,
324 __C0_FUNCT_RESERVED_12,
325 __C0_FUNCT_RESERVED_13,
326 __C0_FUNCT_RESERVED_14,
327 __C0_FUNCT_RESERVED_15,
328 __C0_FUNCT_RESERVED_16,
329 __C0_FUNCT_RESERVED_17,
330 __C0_FUNCT_RESERVED_18,
331 __C0_FUNCT_RESERVED_19,
332 __C0_FUNCT_RESERVED_20,
333 __C0_FUNCT_RESERVED_21,
334 __C0_FUNCT_RESERVED_22,
335 __C0_FUNCT_RESERVED_23,
336 C0_FUNCT_ERET,
337 __C0_FUNCT_RESERVED_25,
338 __C0_FUNCT_RESERVED_26,
339 __C0_FUNCT_RESERVED_27,
340 __C0_FUNCT_RESERVED_28,
341 __C0_FUNCT_RESERVED_29,
342 __C0_FUNCT_RESERVED_30,
343 __C0_FUNCT_RESERVED_31,
344 __C0_FUNCT_RESERVED_32,
345 __C0_FUNCT_RESERVED_33,
346 __C0_FUNCT_RESERVED_34,
347 __C0_FUNCT_RESERVED_35,
348 __C0_FUNCT_RESERVED_36,
349 __C0_FUNCT_RESERVED_37,
350 __C0_FUNCT_RESERVED_38,
351 __C0_FUNCT_RESERVED_39,
352 __C0_FUNCT_RESERVED_40,
353 __C0_FUNCT_RESERVED_41,
354 __C0_FUNCT_RESERVED_42,
355 __C0_FUNCT_RESERVED_43,
356 __C0_FUNCT_RESERVED_44,
357 __C0_FUNCT_RESERVED_45,
358 __C0_FUNCT_RESERVED_46,
359 __C0_FUNCT_RESERVED_47,
360 __C0_FUNCT_RESERVED_48,
361 __C0_FUNCT_RESERVED_49,
362 __C0_FUNCT_RESERVED_50,
363 __C0_FUNCT_RESERVED_51,
364 __C0_FUNCT_RESERVED_52,
365 __C0_FUNCT_RESERVED_53,
366 __C0_FUNCT_RESERVED_54,
367 __C0_FUNCT_RESERVED_55,
368 __C0_FUNCT_RESERVED_56,
369 __C0_FUNCT_RESERVED_57,
370 __C0_FUNCT_RESERVED_58,
371 __C0_FUNCT_RESERVED_59,
372 __C0_FUNCT_RESERVED_60,
373 __C0_FUNCT_RESERVED_61,
374 __C0_FUNCT_RESERVED_62,
375 __C0_FUNCT_RESERVED_63,
376} vr4300_c0_funct;
377
378#define __ASM_I_INST(o, s, t, i) \
379 (((vr4300_instruction_t){.i_type = {.op = (o), .rs = (s), .rt = (t), .imm = (i)&0xFFFF}}).raw)
380#define __ASM_J_INST(o, t) (((vr4300_instruction_t){.j_type = {.op = (o), .target = (t)&0x3FFFFFF}}).raw)
381#define __ASM_R_INST(o, s, t, d, a, f) \
382 (((vr4300_instruction_t){.r_type = {.op = (o), .rs = (s), .rt = (t), .rd = (d), .sa = (a), .funct = (f)}}).raw)
383#define __ASM_C_INST(o, c, f) (((vr4300_instruction_t){.c_type = {.op = (o), .co = (c), .funct = (f)}}).raw)
384
385#define A_OFFSET(a) ((int16_t)((a)&0xFFFF))
386#define A_BASE(a) ((uint16_t)((((a) >> 16) & 0xFFFF) + (A_OFFSET(a) < 0 ? 1 : 0)))
387
388#define I_ADDIU(rt, rs, immediate) __ASM_I_INST(OP_ADDIU, rs, rt, immediate)
389#define I_AND(rd, rs, rt) __ASM_R_INST(OP_SPECIAL, rs, rt, rd, 0, FUNCT_AND)
390#define I_ANDI(rt, rs, immediate) __ASM_I_INST(OP_ANDI, rs, rt, immediate)
391#define I_BEQ(rs, rt, offset) __ASM_I_INST(OP_BEQ, rs, rt, offset)
392#define I_BGTZ(rs, offset) __ASM_I_INST(OP_BGTZ, rs, 0, offset)
393#define I_BNE(rs, rt, offset) __ASM_I_INST(OP_BNE, rs, rt, offset)
394#define I_BNEL(rs, rt, offset) __ASM_I_INST(OP_BNEL, rs, rt, offset)
395#define I_CACHE(op, offset, base) __ASM_I_INST(OP_CACHE, base, op, offset)
396#define I_ERET() __ASM_C_INST(OP_COP0, 1, C0_FUNCT_ERET)
397#define I_J(target) __ASM_J_INST(OP_J, (target >> 2))
398#define I_JR(rs) __ASM_R_INST(OP_SPECIAL, rs, REG_ZERO, REG_ZERO, 0, FUNCT_JR)
399#define I_LBU(rt, offset, base) __ASM_I_INST(OP_LBU, base, rt, offset)
400#define I_LHU(rt, offset, base) __ASM_I_INST(OP_LHU, base, rt, offset)
401#define I_LUI(rt, immediate) __ASM_I_INST(OP_LUI, 0, rt, immediate)
402#define I_LW(rt, offset, base) __ASM_I_INST(OP_LW, base, rt, offset)
403#define I_MFC0(rt, rd) __ASM_R_INST(OP_COP0, COPZ_RS_MF, rt, rd, 0, 0)
404#define I_MTC0(rt, rd) __ASM_R_INST(OP_COP0, COPZ_RS_MT, rt, rd, 0, 0)
405#define I_NOP() __ASM_R_INST(OP_SPECIAL, REG_ZERO, REG_ZERO, REG_ZERO, 0, FUNCT_SSL)
406#define I_OR(rd, rs, rt) __ASM_R_INST(OP_SPECIAL, rs, rt, rd, 0, FUNCT_OR)
407#define I_ORI(rt, rs, immediate) __ASM_I_INST(OP_ORI, rs, rt, immediate)
408#define I_SB(rt, offset, base) __ASM_I_INST(OP_SB, base, rt, offset)
409#define I_SH(rt, offset, base) __ASM_I_INST(OP_SH, base, rt, offset)
410#define I_SRL(rd, rt, sa) __ASM_R_INST(OP_SPECIAL, 0, rt, rd, sa, FUNCT_SRL)
411#define I_SW(rt, offset, base) __ASM_I_INST(OP_SW, base, rt, offset)
412
413#endif /* VR4300_ASM_H__ */
vr4300_op_t
vr4300_op_t
VR4300 Opcode Enumeration.
Definition vr4300_asm.h:53
vr4300_instruction_t::raw
uint32_t raw
Definition vr4300_asm.h:18
vr4300_instruction_t
VR4300 Instruction Structure.
Definition vr4300_asm.h:17
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